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Preliminary
May 2000
PBL 386 65/2 Subscriber Line Interface Circuit
Description
The PBL 386 65/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in DLC, Central Office and other telecommunications equipment. The PBL 386 65/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 65/2 emulates a transformer equivalent dc-feed, programmable between 2x25 and 2x900 , with short loop current limiting adjustable to max 65 mA. A second lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 65/2 is compatible with loop start and ground start signalling. Two- to four-wire and four- to two-wire voice frequency (vf) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable line terminating impedance could be complex or real to fit every market. Longitudinal line voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet the DLC requirements. The PBL 386 65/2 package is 28-pin PLCC and 28-pin SSOP.
Key Features
* Selectable overhead voltage principle - All adaptive: The overhead voltage follows 0.6PeakV < signals < 6.2VPeak. - Semi adaptive: The overhead voltage follows 3.1VPeak < signals < 6.2VPeak. * Metering 2.2 Vrms * High and low battery with automatic switching * Battery supply as low as -10 V * Only +5 V in addition to GND and battery (VEE optional) * 39 mW on-hook power dissipation in active state * Long loop battery feed tracks VBat for maximum line voltage * 44V open loop voltage @ -48V battery feed * Constant loop voltage for line leakage <5 mA * On-hook transmission * Full longitudinal current capability during on-hook
Ring Relay Driver
RRLY
* Programmable loop & ring-trip detector threshold * Ground key detector * Analog temperature guard * Tip open state with ring ground detector * Silent polarity reversal * Line voltage measurement * -40 C to +85 C ambient temperature range
DT DR TIPX RINGX HP TS
Ring Trip Comparator Input Decoder and Control
C1 C2 C3 VCC DET
Ground Key Detector
Two-wire Interface
AOV VBAT2 VBAT
Line Feed Controller and Longitudinal Signal Suppression
PSG LP REF
Off-hook Detector
PLD AGND VTX
38 PB 6L 65 /2
PLC
BGND
VF Signal Transmission
RSN VEE (Optional)
PB
6 L 38
65/
2
Figure 1. Block diagram.
28-pin PLCC and 28-pin SSOP.
1
PBL 386 65/2
Maximum Ratings
Parameter
Preliminary
Symbol
Min
Max
Unit
Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 Power supply, -40C TAmb +85C VCC with respect to A/BGND VEE with respect to A/BGND VBat with respect to A/BGND, continuous VBat with respect to A/BGND, 10 ms VBat2 with respect to A/BGND Power dissipation Continuous power dissipation at TAmb +85 C Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage Ring relay current Ring trip comparator Input voltage Input current Digital inputs, outputs (C1, C2, C3, DET) Input voltage Output voltage (DET not active) Output current (DET) TIPX and RINGX terminals, -40C < TAmb < +85C, VBat = -50V Maximum supplied TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 1 s, tRep > 10 s, Note 2 TIP or RING, pulse < 250 ns, tRep > 10 s, Note 3
TStg TAmb TJ VCC VEE VBat VBat VBat2 PD VG
-55 -40 -40 -0.4 VBat -75 -80 VBat
+150 +110 +140 6.5 0.4 0.4 0.4 0.4 1.5
C C C V V V V V W V V
-5
VCC BGND +13 75 mA
VDT, VDR IDT, IDR VID VOD IOD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA
VBat -5 -0.4 -0.4
VCC 5 VCC VCC 30
V mA V V mA
-110 VBat VBat - 20 VBat - 40 VBat - 70
+110 2 5 10 15
mA V V V V
Recommended Operating Condition
Parameter Symbol Min Max Unit
Ambient temperature VCC with respect to AGND VEE with respect to AGND VBat with respect to BGND VBat2 with respect to BGND
TAmb VCC VEE VBat
-40 4.75 VBat -58 VBat
+85 5.25 -4.75 -10 -10
C V V V V
Notes
1. 2. 3. The circuit includes thermal protection. Operation above max. junction temperature may degrade device reliability. A diode in series with the VBat input increases the permitted continuous voltage and pulse < 10 ms to -85 V. A pulse 1s is increased to the greater of |-70V| and |VBat -40V|. RF1, FR2 20 is also required. Pulse is supplied to TIP and RING outside RF1, FR2.
2
Preliminary
Electrical Characteristics
PBL 386 65/2
-40 C TAmb +85 C, VCC = +5V 5 %, VEE = -5V 5%, VBat = -58V to -40V, RLC=18.7k, IL = 27 mA, ZL = 600 , RF1, RF2 =0 , RRef = 15k, CHP = 68nF, CLP=0.33 F, RT = 120 k, RSG = 24 k, RRX = 120 k, AOV- and VBat2 pin not connected, unless otherwise specified. Current definition: current is positive if flowing into a pin.
Parameter Ref fig Conditions Min Typ Max Unit
Two-wire port Overload level, VTRO ,ILDC 10 mA On-Hook, ILDC 5 mA Input impedance, ZTR Longitudinal impedance, ZLoT, ZLoR Longitudinal current limit, ILoT, ILoR Longitudinal to metallic balance, BLM 2 Active state 1% THD, Note 1 3.1 1.4 35 VPeak VPeak /wire mArms /wire
3
Longitudinal to metallic balance, BLME
3
BLME = 20 * Log
ELO VTR
Note 2 ZT/200 0 < f < 100 Hz 20 active state 28 IEEE standard 455-1985, ZTRX=736, active state Normal polarity: 0.2 kHz < f < 1.0 kHz, Tamb 0-70C 63 1.0 kHz < f < 3.4 kHz, Tamb 0-70C 58 0.2 kHz < f < 1.0 kHz, Tamb -40-85C 58 1.0 kHz < f < 3.4 kHz, Tamb -40-85C 54 Reverse polarity: 0.2 kHz < f < 3.4 kHz, Tamb -40-85C 54 Active state Normal polarity: 0.2 kHz < f < 1.0 kHz, Tamb 0-70C 63 1.0 kHz < f < 3.4 kHz, Tamb 0-70C 58 0.2 kHz f 1.0 kHz, Tamb -40-85C 58 1.0 kHz < f < 3.4 kHz, Tamb -40-85C 54 Reverse polarity: 0.2 kHz < f < 3.4 kHz, Tamb -40-85C 54 Active state Normal polarity: 0.2 kHz < f < 1.0 kHz, Tamb 0-70C 1.0 kHz < f < 3.4 kHz, Tamb 0-70C 0.2 kHz f 1.0 kHz, Tamb -40-85C 1.0 kHz < f < 3.4 kHz, Tamb -40-85C Reverse polarity: 0.2 kHz < f < 3.4 kHz, Tamb -40-85C Active state 0.2 kHz < f < 3.4kHz
dB dB dB dB dB
dB dB dB dB dB
Longitudinal to four-wire balance, BLFE
3
BLFE = 20 * Log
ELO VTX
69 64 64 60 54 40
dB dB dB dB dB dB
Metallic to longitudinal balance, BMLE BMLE = 20 * Log VTR VLO
4
Figure 2. Overload level, VTRO, two-wire port 1 << RL, RL= 600 C
RT = 120 k, RRX = 120 k
C
TIPX
VTX
RL
VTRO
ILDC
PBL 386 65/2
RINGX RSN
RT
E RX
RRX
Figure 3. Longitudinal to metallic (BLME) and Longitudinal to four-wire (BLFE) balance 1 << 150 , RLR = RLT = RL /2= 300 C
RT = 120 k, RRX = 120 k
TIPX ELo C RLT V TR RLR RINGX
VTX
PBL 386 65/2
RSN
RT
V TX
RRX
3
PBL 386 65/2
Ref fig
Preliminary
Conditions Min Typ Max Unit
Parameter
Four-wire to longitudinal balance, BFLE
4
Active state ERX VLo 0.2 kHz < f < 3.4 kHz |ZTR + ZL| r = 20 * Log |ZTR - ZL| BFLE = 20 * Log 0.2 kHz < f < 0.5 kHz 0.5 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz, Note 3 active, IL < 5 mA active, IL < 5 mA tip open, IL < 5 mA active, IL < 5 mA
40
dB
Two-wire return loss, r
25 27 23 - 1.5 VBat + 2.7 VBat + 3.0 VBat +4.2 1.55 0.7 -60 5 -25 GND 10 400
TIPX idle voltage, VTi RINGX idle voltage, VRi RINGX idle voltage, VRi VTR Four-wire transmit port (VTX) Overload level, VTXO, IL 10 mA On hook IL 5 mA Output offset voltage, VTX Output impedance, zTX Four-wire receive port (RSN) Receive summing node (RSN) dc voltage Receive summing node (RSN) impedance Receive summing node (RSN) current (IRSN) to metallic loop current (IL) gain,RSN Frequency response Two-wire to four-wire, g2-4 6 5
dB dB dB V V V V VPeak VPeak mV mV ratio
Load impedance > 20 k, 1% THD, Note 4 0.2 kHz < f < 3.4 kHz IRSN = 0 mA 0.2 kHz < f < 3.4 kHz 0.3 kHz < f < 3.4 kHz
60 20 +25 50
relative to 0 dBm, 1.0 kHz. ERX = 0 V 0.3 kHz < f < 3.4 kHz f = 8.0 kHz, 12 kHz, 16 kHz
-0.15 -0.5
0
0.15 +0.1
dB dB
TIPX C VLo RLT V TR RLR RINGX
VTX
Figure 4. Metallic to longitudinal and four-wire to longitudinal balance
1 << 150 , RLT = RLR = RL /2 =300 C RT = 120 k, RRX = 120 k
RRX
PBL 386 65/2
RSN
RT
E RX
C RL ILDC EL
TIPX
VTX
Figure 5. Overload level, VTXO, four-wire transmit port
1 << RL, RL = 600 C RT = 120 k, RRX = 120 k
RRX
PBL 386 65/2
RINGX RSN
RT
VTXO
4
Preliminary
Parameter Ref fig Conditions Min Typ
PBL 386 65/2
Max
Unit
Four-wire to two-wire, g4-2
6
Four-wire to four-wire, g4-4 Insertion loss Two-wire to four-wire, G2-4
6
relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz f = 8 kHz, 12 kHz, 16 kHz relative to 0 dBm, 1.0 kHz. EL = 0 V 0.3 kHz < f < 3.4 kHz 0 dBm, 1.0 kHz, Note 5 V G2-4 = 20 * Log TX ,ERX = 0 VTR 0 dBm, 1.0 kHz, Notes 5, 6 V G4-2 = 20 * Log TR ,EL = 0 ERX Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -55 dBm to -40 dBm Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -55 dBm to -40 dBm C-message weighting Psophometrical weighting Note 8
-0.15 -1.0 -1.0 -0.15
-0.2 -0.3
0.15 0 0 0.15
dB dB dB dB
6
-6.22
-6.02
-5.82
dB
Four-wire to two-wire, G4-2
6
-0.2
0.2
dB
Gain tracking Two-wire to four-wire RLDC 2k
6
-0.1 -0.2 -0.1 -0.2 7 -83
0.1 0.2 0.1 0.2 12 -78
dB dB dB dB dBrnC dBmp
Four-wire to two-wire RLDC 2k
6
Noise Idle channel noise at two-wire (TIPX-RINGX) Harmonic distortion Two-wire to four-wire Four-wire to two-wire Battery feed characteristics Constant loop current, ILconst 15
6
0 dBm, 1.0 kHz test signal 0.3 kHz < f < 3.4 kHz ILProg = 500 RLC 18 < ILProg < 65 mA S = closed; R = 7 k RLRTO = 0, VBat = -48V RLRTO = 2.5 k, VBat = -48V ILRTO < 23 mA Active state, Tip lead open (S open), Ring lead to ground through 150 Active state, tip lead to -48 V through 7 k (S closed), Ring lead to ground through 150 RL = 0
C
-50 -50
dB dB
0.92 ILProg
ILProg IL 17
Tip open state TIPX current, ILeak Tip open state RINGX current, ILRTO Tip open state RINGX voltage, VRTO Tip voltage (ground start) Tip voltage (ground start)
7 7 7 7 7
1.08 ILProg mA -100 A mA mA V V V
-4 -6
VBat+ 5.8 -2.5 -3.1 -
Open circuit state loop current, ILOC
-100
0
100
A
Figure 6. Frequency response, insertion loss, gain tracking.
RL
TIPX
VTX
1 << RL, RL = 600 C RT = 120 k, RRX = 120 k
VTR EL
ILDC
PBL 386 65/2
RINGX RSN
RT
E RX
VTX
RRX
5
PBL 386 65/2
Ref fig
Preliminary
Conditions Min Typ Max Unit
Parameter
Loop current detector Programmable threshold, IDET Progammable threshold in Tip Open state, IDET
ILTh = 500 RLD 500 ILTh = RLD
0.9*ILTh 0.9*ILTh
ILTh ILTh
1.1*ILTh 1.1*ILTh
mA mA
Ground key detector Ground key detector threshold (ILTIPX and ILRINGX current differance to trigger ground key det.) Line voltage measurement Frequency Ring trip comparator Offset voltage, VDTDR Input bias current, IB Input common mode range, VDT, VDR Ring relay driver Saturation voltage, VOL Off state leakage current, ILk Digital inputs (C1, C2, C3) Input low voltage, VIL Input high voltage, VIH Input low current, IIL Input high current, IIH Detector output (DET) Output low current, IOL Internal pull-up resistor Power dissipation (VBat = -48V; VBat2 = -32V) P1 P2 @ VEE=-5V P3 @ VEE=-48V P4 @ VEE=-5V P5 @ VEE=-5V Power supply currents (VBat = -48V) VCC current, ICC VEE current, IEE VBat current, IBat VCC current, ICC VEE current, IEE VBat current, IBat Power supply rejection ratios VCC to 2- or 4-wire port VEE to 2- or 4-wire port VBat to 2- or 4-wire port VBat2 to 2- or 4-wire port Temperature guard Junction threshold temperature, TJG Thermal resistance 28-pin PLCC, JP28PLCC 28-pin SSOP, JP28SSOP f= 106 |V|TR+1
11
15
19
mA
f
Hz
Source resistance, RS = 0 IB = (IDT + IDR)/2
-20 -50 VBat+1
0 -20
20 200 -1 0.5 100
mV nA V V A V V A A mA k mW mW mW mW mW mA mA mA mA mA mA dB dB dB dB C
IOL = 50 mA VOH = 12 V 0 2.5 VIL = 0.5 VIH = 2.5 V VOL < 0.6V 0.5 1 10 14 39 44 710 340 0.8 -0.15 -0.2 2.0 -0.15 -0.7 28.5 28.5 28.5 28.5 140 39 55 35 55 40 60
0.5 VCC -200 200
Open circuit state Active state ILo = 0 mA, IL = 0 mA Active state ILo = 0 mA, IL = 0 mA Active state RL = 300 (off-hook) Active state RL = 800 (off-hook) Open circuit state Open circuit state Open circuit state Active state ILo= 0 mA, IL = 0 mA Active state ILo= 0 mA, IL = 0 mA Active state ILo= 0 mA, IL = 0 mA Active state, f = 1 kHz, Vn = 100mV Active state, f = 1 kHz, Vn = 100mV Active state, f = 1 kHz, Vn = 100mV Active state, f = 1 kHz, Vn = 100mV
C/W C/W
6
Preliminary
Notes
1. The overload level is automatically expanded when the signal level > 3.1 VPeak and is specified at the two-wire port with the signal source at the four-wire receive port. The two-wire impedance is programmable by selection of external component values according to: ZTR = ZT/|G2-4S RSN| where: ZTR = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G2-4S = transmit gain, nominally = 0.5 RSN = receive current gain, nominally = 400 (current defined as positive flowing into the receivesumming node, RSN, and when flowing from tip to ring). Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground. 4.
PBL 386 65/2
2.
5.
6. 7.
8.
3.
The overload level is automatically expanded, as needed up to 3.1 VPeak when the signal level >1.55 VPeak and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4S = 0.5. Secondary protection resistors RF impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for RF = 0. The specified insertion loss tolerance does not include errors caused by external components. The level is specified at the four-wire receive port and referenced to a 600 programmed two-wire impedance level. The two-wire idle noise is specified with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is the two-wire value -6 dB and is specified with the two-wire port terminated in 600 (RL). The noise specification is referenced to a 600 programmed two-wire impedance level at VTX. The four-wire receive port is grounded (ERX = 0).
R
-48V
S
TIPX
PBL 386 65/2 RLRTO
RINGX
Figure 7. Tipx voltage.
7
PBL 386 65/2
Pin Description
Refer to figure 8.
PLCC SSOP Symbol Description
Preliminary
1 2 3
7 8 9
VBAT VBAT2 AOV
Battery supply voltage. Negative with respect to BGND. An optional second battery voltage, connected in series with a diode, or an external powerhandling resistor connects to this pin. Adaptive Overhead Voltage. If the pin is left open, then the overhead voltage is set internally to 3.1VPeak in off-hook and 1.4 VPeak in on-hook. The overhead voltage will automatically adapt to signals > 3.1VPeak. If the pin is connected to AGND, then no overhead voltage is set internally. The overhead voltage adapts automatically to 0.6 VPeak < signals < 6.2 VPeak. Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a resistor connected from this pin to VBAT. Low Pass filter. Saturation guard filter capacitor connected here to filter out noise and improve PSRR. Other end of CLP connects to VBAT. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The ring trip network connects to this input. -5V to VBAT power supply. A 15 k resistor should be connected between this pin and AGND. Silent Polarity Reversal. The polarity reversal time can be adjusted with a capacitor connected to AGND. If pin is left open: Shortest polarity reversal time. Prog. Line Current, the constant current part of the DC feed characteristic is programmed by a resistor connected from this pin to AGND. Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor connected from this pin to AGND. +5 V power supply. C1, C2 and C3 are digital inputs Controlling the SLIC operating states. Refer to section Operating states for details. No Connect. Must be left open. Detector output. Active low when indicating loop or ring trip detection, active high when indicating ground key detection Receive Summing Node. 400 times the current flowing into this pin equals the metallic (transversal) current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain connect to the receive summing node. Analog Ground, should be tied together with BGND. Transmit vf output. The ac voltage difference between TIPX and RINGX, the ac metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of -0.5. The two-wire impedance programming network connects between VTX and RSN. Ring Relay driver output. Tip Sense should be connected to TIPX. No Connect. Must be left open. High Pass connection for ac/dc separation capacitor CHP. Other end of CHP connects to RINGX. The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). Battery Ground, should be tied together with AGND. The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay).
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
10 11 12 13 16 17 18 19 20 21 22 23 24 14 25 26
PSG LP DT DR VEE REF SPR PLC PLD VCC C3 C2 C1 NC DET RSN
}
20 21
27 28
AGND VTX
22 23 24 25 26 27 28
1 2 15 3 4 5 6
RRLY TS NC HP RINGX BGND TIPX
8
Preliminary
PBL 386 65/2
2 VBAT2
TS 2 HP 3 RINGX 4 BGND 5 TIPX 6 VBAT 7 VBAT2 8 AOV 9 PSG 10 LP 11 DT
12
27 26 25 24 23
AGND RSN DET C1 C2 C3 VCC PLD PLC
LP 5 DT 6 DR 7 VEE 8 REF 9 SPR 10 PLC 11
27 BGND
1 VBAT
28 TIPX
4 PSG
3 AOV
RRLY 1
28
26 RINGX
VTX
25 24 23
HP NC* TS RRLY VTX AGND RSN
28-pin SSOP
22 21 20 19 18
17
28 pin PLCC
22 21 20 19
PLD 12
VCC 13
C3 14
C2 15
C1 16
NC* 17
REF VEE NC*
DR 13 *NC
14
16
15
* Pins must be left open.
Figure 8. Pin configuration 28 pin SSOP and 28 pin package, top view.
SLIC Operating States
State 0 1 2 3 4 5 6 7 C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 0 1 0 1 0 1 0 1 SLIC operating state Open circuit Ringing state Active state Active state Tip open state Active state Active reverse Active reverse Active detector Detector is set high Ring trip detector (active low) Loop detector (active low) Line voltage measurement Loop detector (active low) Ground key detector (active high) Loop detector (active low) Ground key detector (active high)
Table 1. SLIC operating states.
DET 18
SPR
9
PBL 386 65/2
Preliminary
+
ZL VTR
TIP RF ZTR
TIPX
IL
EL
RHP
+ G2-4S IL
VTX
+
VTX
-
+
RING
RF RINGX ZT
-
Z RX RSN I L / RSN
+
VRX
PBL 386 65/2
Figure 9. Simplified ac transmission circuit.
-
Functional Description and Applications Information Transmission
General A simplified ac model of the transmission circuits is shown in figure 9. Circuit analysis yields: VTX VTR = (1) - I * 2RF G2-4S L VTX VRX I (2) + =L ZRX RSN ZT VTR = IL * ZL - EL (3) VRX is the analogue ground referenced receive signal. RSN is the receive summing node current to metallic loop current gain. The nominal value of RSN =400 Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the fuse resistor RF, let VRX = 0. From (1) and (2): ZT ZTR = - 2RF RSN * G2-4S Thus with ZTR, G2-4S, RSN, and RF known: ZT = RSN * G2-4S * (2RF - |ZTR|) Two-Wire to Four-Wire Gain From (1) and (2) with VRX = 0: G2-4 = VTX = VTR ZT/RSN ZT - 2RF RSN * G2-4S Four-Wire to Two-Wire Gain From (1), (2) and (3) with EL = 0: G4-2 = VTR ZT ZL * = VRX ZRX ZT - G2-4S * ( ZL + 2RF) RSN
where: VTX is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals. VTR is the ac metallic voltage between tip and ring. EL is the line open circuit ac metallic voltage. IL is the ac metallic current. RF is a fuse resistor. G2-4S is the SLIC two-wire to fourwire gain (transmit direction) with a nominal value of -0.5. (Phase shift 180) ZL is the line impedance. ZT determines the SLIC TIPX to RINGX impedance for signal in the 0 - 20kHz frequency range. ZRX controls four- to two-wire gain.
In applications where 2RF - ZT/(RSN * G2-4S) is chosen to be equal to ZL, the expression for G4-2 simplifies to: G4-2 = ZT 1 * ZRX 2 * G2-4S
Four-Wire to Four-Wire Gain From (1), (2) and (3) with EL = 0: G4-4 = G2-4S * ( ZL + 2RF) VTX ZT * = VRX ZRX ZT - G2-4S * ( ZL + 2RF) RSN
10
Preliminary
Hybrid Function The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 10. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting: VTX VRX + = 0 (EL = 0) RTX ZB The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from: V ZB = - RTX * RX = VTX ZT RSN - G2-4S * ( ZL + 2RF) G2-4S * ( ZL + 2RF) The PBL 386 65/2 SLIC may also be used together with programmable CODEC/ filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, ZLoT and ZLoR, appears as typically 20 to longitudinal disturbances. It should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Capacitors CTC and CRC If RFI filtering is needed, the capacitors designated CTC and CRC in figure 13, connected between TIPX and ground as well as between RINGX and ground, may be mounted. CTC and CRC work as RFI filters in conjunction with suitable series impedances (i.e. resistances, inductances). Resistors
PBL 386 65/2
RF1 and RF2 may be sufficient, but series inductances can be added to form a second order filter. Current-compensated inductors are suitable since they suppress common-mode signals with minimum influence on return loss. Recommended values for CTC and CRC are below 1 nF. Lower values impose smaller degradation on return loss and longitudinal balance, but also attenuate radio frequencies to a smaller extent. The influence on the impedance loop must also be taken into consideration when programming the CODEC. CTC and CRC contribute to a metallic impedance of 1/(*f*CTC) = 1/(*f*CRC), a TIPX to ground impedance of 1/(2**f*CTC) and a RINGX to ground impedance of 1/(2**f*CRC). AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and RINGX p r o vides the separation of the ac and dc signals. CHP positions the low end frequency response break point of the ac loop in the SLIC. Refer to table 1 for recommended value of CHP. Example: A CHP value of 68 nF will position the low end frequency response 3dB break point of the ac loop at 13 Hz (f3dB) according to f3dB = 1/(2**RHP*CHP) where RHP = 180 k.
Z - RTX * RX * ZT
When choosing RTX, make sure the output load of the VTX terminal is > 20 k. If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended.
RFB
VTX
RTX VT ZT Z RX ZB
PBL 386 65/2
Combination CODEC/Filter
V RX
RSN
Figure 10. Hybrid function.
11
PBL 386 65/2
High-Pass Transmit Filter When CODEC/filter with a singel 5 V power supply is used, it is necessary to separate the different signal reference voltages between the SLIC and the CODEC/filter. In the transmit direction this can be done by connecting a capacitor between the VTX output of the SLIC and the CODEC/filter input. This capacitor will also form, together with RTX and/or the input impedance of the CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a fast enough response for the dc steps that may occur with DTMF signaling.
Preliminary
Capacitor CLP The capacitor CLP, which connects between the terminals LP and VBAT, positions the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with CHP and ZT (see section TwoWire Impedance) forms the total two wire output impedance of the SLIC. The choice of these programming components influence the power supply rejection ratio (PSRR) from VBAT to the two wire side in the low frequency range. RFeed RSG CLP CHP [] [k] [nF] [nF] 4.02 330 68 2*25 2*50 23.7 330 68 2*200 147 100 33 2*400 301 47 33 2*800 619 22 33 Table 1. RSG, CLP and CHP values for different feeding characteristics. Table 1 suggest values of CLP and CHP for different feeding characteristics. Adaptive Overhead Voltage, AOV The Adaptive Overhead Voltage feature minimises the power dissipation and at the same time provides a flexible solution for differing system requirements and possible future changes concerning voice, metering and other signal levels. This is done by using an overhead voltage which automatically adapts to the signal level (voice + metering). With the AOV-pin left open, the PBL 386 65/2 will behave as a SLIC with fixed overhead voltage for signals in the 0 - 20kHz frequency range and with an ampli-
Figure 11. The AOV funktion when the AOV-pin is left open. (Observe, burst undersampled).
tude less than 3.1VPeak11. For signal amplitudes between 3.1VPeak and 6.2VPeak, the AOV-function will expand the overhead voltage making it possible for the signal, Vt, to propagate through the SLIC without distortion (see figure 11). The expansion of the overhead voltage occurs instantaneously. When the signal amplitude decreases, the overhead voltage returns to its initial value with a time constant of approximately one second. If the AOV-pin is connected to AGND, the overhead voltage will automatically be adjusted for signal levels between 0.6 VPeak and 6.2 VPeak. AOV In the Constant Current Region When the overhead voltage is automatically increased, the apparent battery (VApp, reference F in figure 15), will be reduced by the signal amplitude minus 3.1 VPeak(11), (Vt - 3.1(11)). In the constant current region this change will not affect the line current as long as VTR < VApp - (ILConst * RFeed) - (Vt-3.1(11)), (references A-C in figure 15). AOV In the Resistive Loop Feed Region The saturation guard will be activated when the SLIC is working in the resistive loop feed region, i.e. VTR > VApp - (ILConst * RFeed) - (Vt - 3.1(11)) (references D in figure 15). If the signal amplitude is greater than 3.1VPeak11 the line current, IL, will be reduced corresponding to the formula IL = | (Vt - 3.1(11))/(RL + RFeed) |. This reduction of line current will introduce a transversal signal into the two-wire which under some circumstances may be audible (e g when sending metering signals > 3.1 VPeak without any speech signal burying the transversal signal generated from the linecurrent reduction). The sum of all signals should not exceed 6.2 VPeak.
Line Feed
If VTR < VApp - (ILConst * RFeed), the PBL 386 65/ 2 SLIC will emulate constant current feed (references A-C in figure 15). For VTR > VApp - (ILConst * RFeed) the PBL 386 65/2 SLIC will emulate resistive loop feed programmable between 2*25 12 and 2*900 (references D in figure 15). The current limitation region is adjustable between 0 mA and 65 mA13. When the line current is approaching open loop conditions, the overhead voltage is reduced. To ensure maximum open loop voltage, even with telephone line leakage, this occurs at a line current of approximately 5 mA (references E in figure 15). After the overhead voltage reduction, the line voltage is kept nearly constant with a steep slope corresponding to 2 * 25 (reference G in figure 15). The open loop voltage, VTRMax, measured between the TIPX and RINGX terminals is tracking the battery voltage VBat (references H in figure 15). VTRMax is programmable by connecting the AOV-pin to AGND or by leaving the AOV-pin open.
12
Preliminary
VTRMax is defined as the battery voltage on the VBat terminal minus the Battery Over Head voltage, VBOH, according to the equation VTRMax(at IL = 0 mA) = |VBat| - VBOH Refer to table 2 for typical VBOH values. VBOH(typ) [V] AOV-PIN NC 4.2 AOV-PIN to AGND 3.2 Table 2. The battery overhead voltages at open loop conditions. Resistive Loop Feed Region The resistive loop feed (reference D in figure 15) is programmed by connecting a resistor RSG , between terminals PSG and VBAT according to the equation RFeed = RSG + 40 + 2RF 400
PBL 386 65/2
Figure 12. Silent Polarity Reversal
Constant Current Region The current limit (reference C in figure 15) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: RLC = 500 ILProg
14
Battery Switch (VBAT2) To reduce short loop power dissipation, a second lower battery voltage may be connected to the device through an external diode at terminal VBAT2. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching occurs when the line voltage passes the value VTR = |VBat2| - 40*IL - 6 15 Connect the terminal VBAT2 to the second power supply via the diode DB2 in figure 14. An optional diode DBB connected between terminal VBAT and the VB2 power supply, see figure 13, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears.
If the VB2 voltage is not available, an optional external power management resistor, RPM, may be connected between the VBAT2-pin and the VBAT-pin to move power dissipation outside the chip. Calculation of the external power management resistor to locate the maximum power dissipation outside the SLIC is according to: RPM = |VBat| - 3 ILProg
where: VTTX is the voltage of the signal at the metering generator, ZLTTX is the line impedance seen by the 12 or 16 kHz metering signal, G2-4S is the transmit gain through the SLIC, i e -0.5. (Phase shift 180) In metering applications with resistive line feeding characteristic and very strict requirements (as mentioned earlier in chapter "AOV in resistive loop feed region"), the metering signal level should not exceed 2.2 VRMS 16, since a reduction of the line current will generate a transversal, and sometimes audible, signal (which is not the case in the constant current region).
Metering Applications, TTX
It is very easy to use PBL 386 65/2 in metering applications; simply connect a suitable resistor (RTTX) in series with a capacitor (CTTX) between pin RSN and the metering source. Capacitor CTTX decouples all DC-voltages that may be superimposed on the metering signal. Choose 1/ (2RTTXCTTX) 5kHz to suppress low frequency disturbances from the metering puls generator. The metering signal gain can be calculated from the equation: G4-2TTX = ZT * RTTX VTR = VTTX ZLTTX
Silent Polarity Reversal
The reversal time is set by a capacitor, Csprv, between the pin SPR and AGND. The reversal has a setup time and reversal time see figure 12. The setup time is different in Active- to Reversal-state and Reversal- to Active state but the silent polarity reversal time is the same Active- to Reversal-state and Reversal- to Active state. To calculate the silent polarity reversal time use following formula: tr =CSPR . 9500
RSN
ZT
- G2-4S * (ZLTTX + 2RF)
13
PBL 386 65/2
Preliminary
R FB
PBL 386 65/2
KR
RRLY VTX AGND RSN DET NC C1 C2 C3 VCC PLD PLC SPR REF VEE
R TX RT RB + out
+12 V /+5V
C GG R F1 C RC VB C TC D B2 C HP
TS NC
R RX
RING
HP RINGX BGND TIPX VBAT VBAT2
out CODEC/ Filter
OVP TIP R F2
VB2 DB VB CB R1 E RG R RF R RT R2 C LP D BB C B2 R SG
VCC
R LD R LC SYSTEM CONTROL INTERFACE
AOV PSG LP DR DT
R REF VEE
C1
R3
R4
C2
+5 V C VCC
VCC
C VEE VBATRESISTORS: (Values according to IEC-63 E96 series) RSG RLD RLC RREF RT RTX RB RRX RFB R1 R2 R3 R4 RRT RRF RF1, RF2 = 23.7 k 1% 1/10 W = 49.9 k 1% 1/10 W = 18.7 k 1% 1/10 W = 15 k 1% 1/10 W = 105 k 1% 1/10 W = 32.4k 1% 1/10 W = 57.6k 1% 1/10 W = 105k 1% 1/10 W Depending on CODEC / filter = 604 k 1% 1/10 W = 604 k 1% 1/10 W = 249 k 1% 1/10 W = 280 k 1% 1/10 W = 332 5% 2 W = 332 5% 2 W = Line resistor, 40 1%
CAPACITORS:(Values according to IEC-63 E6 series) CB CB2 CVCC CVEE CTC CRC CHP CLP CGG C1 C2 = 100 nF = 150 nF = 100 nF = 100 nF = 1 nF = 1 nF = 68 nF = 330 nF = 220 nF = 330 nF = 330 nF 100 V 20% 100 V 20% 10 V 20% 10 V* 20% 100 V 20% 100 V 20% 100 V 20% 100 V 20% 100 V 20% 63 V 10% 63 V 10%
DIODES:
DB DB2 DBB
= 1N4448 = 1N4448 = 1N4448 (optional)
OVP: Secondary protection (eg Power Innovations TISP PBL2). The ground terminals of the secondary protection should be connected to the common ground on the Printed Board Assembly with a track as short and wide as possible, preferably a groundplane.
*100V if VEE pin connected to VBAT, VBAT2
Figure 13. Single-channel subscriber line interface with PBL 386 65/2 and combination CODEC/filter
Active- to Reversal-state and Reversalto Active state and the setup time use following formulas. Active Reversal: tAct Rev = CSPR . 17500 Reversal Active: tRev Act = CSPR . 15500 The time is measured between 10% and 90% of the line voltage. The reversal time is independent of line load and line current.
Analog Temperature Guard
The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 65/2 SLIC reduces the dc line current and the longitudinal current limit when the chip temperature reaches approximately 145C and increases it again automatically when the temperature drops. The detector output, DET, is forced to a logic low level when the temperature guard is active.
Loop Monitoring Functions
The loop current, ground key and ring trip detectors report their status through a common output, DET. The status of the detector pin, DET, is selected via the three bit control interface C1, C2 and C3. Please refer to section Control Inputs for a description of the control interface. Loop Current Detector The loop current detector indicates that the telephone is off hook and that DC current is flowing in the loop by putting the output pin
14
Preliminary
PBL 386 65/2
ined by a software routine to determine the duty cycle. Off-hook condition is indicated when the DET output is at logic level low for more than half the time. Line Voltage Detector The line voltage is presented on the detector output as a pulse train (see figure 15) with a frequency inversely proportional to the voltage according to the equation: 106 [Hz] freq = |VTR| + 1 The line voltage measurement will be started when entering this state from any other state.
Detector Output (DET)
Figure 14. Line voltage Measurement
DET, to a logic low level when selected. The loop current detector threshold value, ILTh, where the loop current detector changes state, is programmable with the RLD resistor. RLD connects between pin PLD and ground and is calculated according to: RLD = 500 ILTh The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the on-hook state no dc current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay is energized, dc current flows and the comparator input voltage reverses polarity. Figure 13 gives an example of a ring trip detection network. This network is applicable, when the ring voltage superimposed on the battery voltage is injected on the ring lead of the two-wire port. The dc voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the filter network R1, R2, R3, R4, C1 and C2. DT is more positive than DR, with the line on-hook (no dc current). The DET output will report logic level high, i.e. the detector is not tripped. When the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor RRT and will cause the input DT to become more negative than input DR. This changes the output on the DET pin to logic level low, i.e. tripped detector condition. The system controller (or line card processor) responds by de-energizing the ring relay via the SLIC, i.e. ring trip. Complete filtering of the 20 Hz ac component at terminals DT and DR is not necessary. A toggling DET output can be examThe PBL 386 65/2 SLIC incorporates a detector output driver designed as open collector (npn) with a current sinking capability of min 3 mA, and a 5 k pull-up resistor. The emitter of the drive transistor is connected to AGND. A LED can be connected in series with a resistor (1 k) at the DET output to visualize, for example loop status.
Relay driver
The PBL 386 65/2 SLIC incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50 mA.The emitter of the drive transistor is connected to BGND. The relay driver has an internal zener diode clamp to protect the SLIC from inductive kick-back voltages. No external clamp is needed.
The current detector is internally filtered and is not influenced by the ac signal at the two wire side. Ground Key Detector The ground key detector indicates when the ground key is pressed (active) by putting the output pin DET to a logic high level when selected. The ground key detector circuit senses the difference between TIPX and RINGX currents. The detector is triggered when the difference exceeds the current threshold. Ring Trip Detector Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced e g superimposed on the battery voltage or ground. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to tip and ring.
Control Inputs
The PBL 386 65/2 SLIC has three digital control inputs, C1, C2 and C3. A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. C1 to C3 are internal pull-up inputs. Open Circuit State In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum and no detectors are active.
15
PBL 386 65/2
Preliminary
DC characteristics
A B C B C
D
D
I L [mA]
E J G
F
H
F
V T R [V]
A:
IL (@ VTR = 0) = ILConst
ILConst (typ) = ILProg =
500 RLC (14)
B, C: IL = ILConst D: E: F: G: H: J: RFeed =
VTR = VBatVirt - RFeed * (ILProg - 5*10-3)
RSG + 40 400 IL 5 mA Apparent battery VApp (@IL = 0) = VBatVirt + 5*10-3 * RFeed RFeedG = 2 * 25 VTRMax = |VBat| - VBOH Virtual battery VBatVirt (@ IL = 5 mA) = |VBat| - 6.8(17)
Figure 15. Battery feed characteristics (without the protection resistors on the line).
Ringing State In the ringing state the SLIC will behave as in the active state with the exception that the ring relay driver and the ring trip detector are activated. The ring trip detector will indicate off hook with a logic low level at the detector output.
Active State TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. The loop current or the ground key detector is activated. The loop current detector indicates off hook with a logic low level and the ground key detector indicates active ground key with a logic high level present at the detector output.
Active Line Voltage State In PBL 386 65/2 a line voltage measurement feature is available in the active state. A frequency inversely proportional to the line voltage is presented on the detector output (see chapter "Line Voltage Detector"). The data can be used in a variety of ways, for example to set transmission parameters in a programmable CODEC, inline testing where short circuits on the line can be detected and to control the metering signal amplitude. In the active line voltage state the SLIC will be as in the active state except for the detector.
16
Preliminary
Active Polarity Reversal State TIPX and RINGX polarity is reversed compared to the Active State: RINGX is the terminal closest to ground and sources loop current while TIPX is the more negative terminal and sinks current. The loop current or the ground key detector is activated. The loop current detector will indicate off hook with a logic low level and the ground key detector will indicate active ground key with a logic high level present at the detector output. Tip Open State The Tip Open State is used for ground start signaling. In this state the SLIC presents a high impedance on the TIPX pin and the programmed dc characteristic on the RINGX pin, without the longitudinal current compensation. The loop current detector is active (refer to the datasheet for information on the detector threshold level). A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. CGG should be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the VB supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors RF serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. If a PTC is chosen for RF , note that it is important to always use the PTCs in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the TISP.
PBL 386 65/2
Notes
Note 11. 3.1 VPeak if AOV-pin is left open and 0.6 VPeak if AOV-pin is connected to AGND. Note 12. RFeed lower than 2x50 will reduce noise and PSRR performance in resistive loop region (reference D in figure 15). Better PSRR performance can be achieved by increasing CLP and CHP. Note 13. If the momentary value of the current in TIPX-pin or RINGX-pin exceeds 85mA harmonic distortion specification can be derated. Note 14. The accurate equation for RLC is:
RLC = 500 10.4 * In (ILProg * 32) ILProg ILProg
Power-up Sequence
No special power-up sequence is necessary except that ground has to be present before all other power supply voltages. The digital inputs C1 to C3 are internal pull-up terminals.
Overvoltage Protection
PBL 386 65/2 must be protected against overvoltages on the telephone line. The overvoltages could be caused for instance by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum continuous and transient voltages. Secondary Protection The circuit shown in figure 13 utilizes series resistors together with a programmable overvoltage protector (e g Power Innovations TISP PBL2), serving as a secondary protection. The TISP PBL2 is a dual forward-conducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i.e. the battery voltage, VB). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor.
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout is essential for proper function; The components connecting to the RSN input should be placed in close proximity to that pin, such that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point. RLC and RREF should be connected to AGND with short leads. Pin LP, pin PSG and pin AOV are sensitive to leakage currents. Pin AOV should be surrounded by a guardring connected to AGND. RSG and CLP connections to VBAT should be short and very close to each other. CB and CB2 must be connected with short wide leads.
Note 15. 6.0V when AOV-pin is not connected, 3.9V when AOV-pin is connected to AGND.
Note 16. 2.2VRMS if AOV-pin is left open and 0.4VRMS if AOV-pin is connected to AGND.
Note 17. 6.8V when AOV-pin is left open, 4.2V when AOV-pin is connected to AGND.
17
PBL 386 65/2
Preliminary
Ordering Information
Package Temp. Range Part No.
28pin PLCC Tube
-40 - +85 C PBL 386 65/2QNS
28pin PLCC Tape & Reel -40 - +85 C PBL 386 65/2QNT 28pin SSOP Tape & Reel -40 - +85 C PBL 386 65/2SHT
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice. 1522-PBL 386 65/2 Uen Rev. F (c) Ericsson Microelectronics AB, 2000 This product is an original Ericsson product protected by US, European and other patents.
Ericsson Microelectronics AB SE-164 81 Kista, Sweden Telephone: +46 8 757 50 00 18

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